1. Field of the Invention
The present invention relates to an address decoder in a synchronous memory module such as a synchronous high-speed SRAM module or the like.
2. Description of the Related Art
A synchronous memory module (which will be hereinafter referred to as a "module") has following various operations. First of all, it executes an operation of selecting a memory cell within the module, corresponding to a specified address determined by address data consisting of a plurality of externally inputted address signals. Secondly, it executes a reading operation for reading data stored in the selected memory cell and outputting the data out of the module, and thirdly it executes a writing operation for writing data inputted from an exterior of the module into the memory cell of the specified address.
In a synchronous high-speed SRAM module, following operations must be executed and completed at high speed within one cycle of a system clock (which will be hereinafter referred to as a "clock").
Namely, they are an operation of continuously selecting a memory cell and reading data from the memory cell, and an operation of continuously selecting a memory cell and writing data into the memory cell.
Within the module, the memory cells are formed as a memory array in such a manner as to be uniformly and densely arranged both in vertical and horizontal directions. The operation of selecting a memory cell of the specified address in the memory array includes a row (word) selecting operation for selecting the horizontal direction of the array from a plurality of address signals inputted from the exterior of the module and a row selecting operation for selecting the vertical direction of the array from these address signals. The above-described address decoder is used to decode address data consisting of a plurality of address signals and select only one word within the memory array.
FIG. 20 is a circuit diagram which shows an example of a conventional address decoder. The address decoder includes a control circuit 1001, an address driver 1002, and a decoding circuit row i consisting of 256 decoding circuits i.sub.0 through i.sub.255.
The address driver 1002 generates drive signals d.sub.n and rd.sub.n (n=0, 1 . . . 7) which are positive-phase and negative-phase signals of an input address signal A.sub.n (n=0, 1 . . . 7).
FIG. 21 is a circuit diagram which shows a structural example of the address driver 1002. Driving circuits D.sub.0 through D.sub.7 provided to respectively correspond to address signals A.sub.0 to A.sub.7 all have the same circuit structure. In the drive circuit D.sub.n corresponding to the address signal A.sub.n, a D-type flip-flop circuit (F/F circuit) 200 latches the address signal A.sub.n at a rising edge of a clock signal CK. Output of the F/F circuit 200 is outputted as the drive signal d.sub.n via NOT circuits 201, 202, and is further outputted as the drive signal rd.sub.n via a NOT circuit 203. Namely, the drive signal d.sub.n outputs a logical level of the same phase as that of the address signal A.sub.n and the drive signal rd.sub.n outputs a logical level whose phase is opposite to that of the logical level of the address signal A.sub.n.
The control circuit 1001 inputs an externally inputted clock signal CK, a function selecting signal SEL which designates operation of the module, and a reading operation signal SAD from the memory module. The control circuit 1001 generates, from these input signals, an enable signal EN which permits or prohibits operation of the decoding circuit row i, and a pre-charge signal NPR which controls reading and/or writing operation of the memory module.
FIG. 22 is a circuit diagram which shows a structural example of the control circuit 1001. In this figure, F/F circuit 100 latches the function selecting signal SEL at the rising edge of the clock signal CK to generate the pre-charge signal NPR. Further, a NAND circuit 102 to which an inverted signal of the pre-charge signal NPR is inputted and a NAND circuit 103 to which an inverted signal of the reading operation signal SAD is inputted composes an SR latch circuit, and output of the NAND circuit 103 forms an output terminal of the enable signal EN.
The decoding circuit row i selects, by the decoding circuits i.sub.0 through i.sub.255, one word line among 256 word lines W.sub.0 through W.sub.255, which are designated by 16 drive signals d.sub.0 through d.sub.7 and rd.sub.0 through rd.sub.7 inputted from the address driver 1002. These decoding circuits i.sub.0 through i.sub.255 have the same circuit structure, each having eight input terminals I.sub.0 through I.sub.7. When the logical level of the enable signal EN is "0", the decoding circuit i.sub.m (m=0, 1 . . . 255) outputs logical product (the AND) of eight input signals to the word line W.sub.m, and when the logical level of the enable signal EN is "1", the decoding circuit i.sub.m outputs a logical level "0" to the word line W.sub.m irrespective of each logical level of the input signals.
In FIG. 20, 256 word lines W.sub.0 through W.sub.255 are used to select a row (word) of a memory array (not shown, but the memory array described herein consists of 256 words) in which memory cells are arranged in the form of an array. The word line W.sub.m is connected to a selection gate (not shown) of a memory cell of a corresponding word. When data consisting of address signals A.sub.0 through A.sub.7 is the one that indicates an address space of the m-th address (i.e., a word of the m-th address) within the memory array (in this case, it is assumed that a depth-wise direction for 1-bit data to be written into/read from the module is given as 256, i.e., the number of row is given as 1), the decoding circuit i.sub.m outputs and selects a logical level "1" to the word line W.sub.m corresponding to the word. Accordingly, when data consisting of the address signals A.sub.0 through A.sub.7 indicates the m-th address, the input terminal I.sub.n of the decoding circuit i.sub.m, which corresponds to the address signal A.sub.n having the logical level "1", is connected to the drive signal d.sub.n and the input terminal I.sub.n of the decoding circuit i.sub.m, which corresponds to the address signal A.sub.n having the logical level "0", is connected to the drive signal rd.sub.n.
Next, a decoding operation of the address decoder shown in FIG. 20 will be described. FIG. 23 is an operational timing chart of the address decoder shown in FIG. 20. Note that only the decoding operation in a data reading cycle will be described hereinafter, and a description of the decoding operation in a data writing cycle which is similar to the above will be omitted.
In a waiting state in which the function selecting signal SEL is "0", the pre-charge signal NPR has a logical level "0", the reading operation signal SAD has a logical level "0", and the enable signal EN has a logical level "1".
When the function selecting signal SEL becomes "1", in FIG. 22, the F/F circuit 100 latches the function selecting signal SEL at the rising edge of the clock signal CK so that the pre-charge signal NPR becomes "1" to be brought into a discharge state. When the pre-charge signal NPR changes as described above, output of the NOT circuit 101 becomes "0", output of the NAND circuit 102 changes to "1", and three inputs of the NAND circuit 103 all become "1", so that the enable signal EN changes to "0".
In accordance with the logical levels of the drive signals d.sub.0 through d.sub.7 and rd.sub.0 through rd.sub.7 from the address driver 1002, only one decoding circuit i.sub.m outputs "1" to the word line W.sub.m and a memory cell connected to the word line W.sub.m is thereby selected. When reading of data from the memory cell is completed, the module allows the reading operation signal SAD to be set to be "1".
As a result, in FIG. 22, output of the NOT circuit 104 becomes "0", and therefore, output of the NAND circuit 103 changes to "1" and the enable signal EN returns to "1". Further, since three inputs of the AND circuit 105 all becomes "1", output of the AND circuit 105 becomes "1", the F/F circuit 100 is reset, and the pre-charge signal NPR returns to "0" to be brought into a pre-charge state. As a result, the decoding operation of one cycle is completed.
The synchronous high-speed. SRAM executes operations for writing and reading data into and from a memory cell during one clock cycle. In either case, it is necessary for the SRAM to complete these operations within one clock cycle starting from inputting of the address signals A.sub.n and to return to a waiting state for the subsequent one clock cycle. At this time, an access-cycle start condition is supplied from the exterior of the module, but a timing element for controlling the interior of the memory module cannot be supplied from the exterior of the module. For this reason, if necessary, there is no alternative but to generate the timing element within the module. Accordingly, the operation within the module must be constructed by asynchronous logics.
In the address decoder of the synchronous memory module like the above, supply of the drive signals for a large number of uniformly arranged decoding circuits allows driving of a long wire connected to a large number of loads, i.e., driving of a large load capacity. At this time, a wave form of a signal which reaches a decoding circuit located at a leading end portion of a drive signal line from the address driver delays greatly as compared with a decoding circuit located near to the address driver.
Accordingly, there is a possibility that the phase relationship of the enable signal EN and the drive signals d.sub.n and rd.sub.n greatly differs between the decoding circuit near to the address driver and the decoding circuit located at the leading end portion of the drive signal line. For this reason, it is not possible to ensure whether or not the set-up time and holding time of the address signals A.sub.n with respect to the enable signal EN is secured. In other words, the drive signals d.sub.n and rd.sub.n may change in a period in which the enable signal EN is "0". Accordingly, there is a possibility that a plurality of word lines may be temporarily selected and a wrong word (memory cell) may thereby be selected. When illustrated with reference to FIG. 23, in the decoding circuit located at the leading end portion of the drive signal line, there is a possibility that the enable signal EN may become "0" before the drive signals d.sub.n and rd.sub.n change.
In the address decoder, it is necessary to secure the set-up time which indicates how long it takes from the time of the address signal being fixed to the falling edge of the enable signal EN, and the holding time which indicates how long it takes from the rising edge of the enable signal to the time when the logical level of the address signal changes.
As described above, the conventional address decoder has a problem in that it is not possible to sufficiently secure the set-up time and a malfunction thereby occurs in which read data from the memory cell is brought into an abnormal logical level.